1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a nonvolatile memory and an apparatus and method for deciding data validity for the same, and more particularly, to a nonvolatile memory and an apparatus and method for deciding data validity for the same, in which validity of data stored in the nonvolatile memory can be decided.
2. Description of the Related Art
Generally, embedded systems, such as electric home appliances, communication devices, and set top boxes, widely employ a nonvolatile memory as a storage medium that stores data.
A flash memory, which is mainly used as the nonvolatile memory, is a nonvolatile memory device that can electrically erase or rewrite data. Such a flash memory is suitable for a portable device due to its lower power consumption than a storage medium based on a magnetic disk memory, its fast access time equal to that of a hard disk, and its small size.
A basic mechanism for storing data bits in the aforementioned nonvolatile memory is a memory cell. The memory cell is composed of a single field effect transistor which includes a control gate, a floating gate, a source, and a drain. In this case, data bits are stored in the nonvolatile memory by changing a charge amount on the floating gate to change a threshold voltage of the memory cell. Also, the memory cell reads a voltage by selectively applying the voltage through a wordline of the control gate.
The memory cell provides storage ability capable of storing two states through one bit. In other words, the memory cell provides storage ability capable of storing either a bit of “1” or a bit of “0” in response to the applied voltage, wherein the bit of “1” corresponds to the state that the data are erased, and the bit of “0” corresponds to the state that the data are stored.
At this time, since essential requirements for a large sized memory device realize the low cost per bit, studies for storing data of a number of bits in one memory cell are actively in progress.
A technique that can remarkably reduce the cost per bit in a nonvolatile memory has been disclosed in “A Multilevel-Cell 32 Mb Flash Memory” in IEEE, ISSCC Digest of Technical Papers, pp. 132-133 by M. Bauer, et al. on February in 1995. This reference includes the technique for providing storage ability of four states through two bits per memory cell.
As described above, the nonvolatile memory having storage ability of four states through two bits per memory cell will be referred to as a multi level cell (MLC) nonvolatile memory. This MLC nonvolatile memory stores data bits corresponding to two pages through one memory cell. Also, the two pages corresponding to one memory cell will be referred to as least significant bit (LSB) page and most significant bit (MSB) page, respectively, and the data bits are stored from the LSB page.
In more detail, the MLC nonvolatile memory has four states S0, S1, S2, and S3 realized by two bits as shown in FIG. 1, wherein each state is composed of a pair of data bits of LSB page and MSB page. If a block of the nonvolatile memory is erased, every memory cell in the block has the state S0. At this time, if the data bits are written in the LSB page, the state is changed to the state S1. Again, if the data bits are written in the MSB page, the state is changed from S1 to S2. Meanwhile, the state is changed from S0 to S3 through the states S0, S1 and S2.
A time period T3 is required to change the state from S0 to S3 after a time period T1 and a time period T2 pass, wherein the time period T1 is required to change the state from S0 to S1 and the time period T2 is required to change the stage from S1 to S2. Accordingly, the time period T3 is longer than the time period T1.
Unexpected power failure frequently occurs in a system based on the nonvolatile memory in view of the application field of the system. Accordingly, steps to be taken against the power failure occurring in the middle of the operation of the nonvolatile memory will essentially be required.
FIG. 2 is a view illustrating the structure of a related art nonvolatile memory.
The general nonvolatile memory 10 is composed of a plurality of blocks 11 which include a plurality of pages 12. The respective blocks 11 have sizes of 16 KB, 64 KB, 128 KB, and 256 KB, wherein the sizes are decided by the number of pages included in the blocks and the size of each page. The blocks 11 are erasing units in the general nonvolatile memory 10, and the pages 12 are writing units therein.
If the power failure occurs in the middle of data writing in the general nonvolatile memory 10, the data to be written may not completely be written. Accordingly, when referring to the written data later, it is necessary to first decide whether the data are valid. To decide validity of the data, mirror data of the data whose validity is to be decided will be written together.
Specifically, as shown in FIG. 3, mirror data 22 and 23 of actual data 21 are written in a page 20 included in a predetermined block along with the actual data 21, so that the mirror data 22 and 23 are compared with the actual data 21 to decide validity of the data. If the mirror data 22 and 23 are equal to the actual data 21, it is decided that the actual data 21 are valid. Otherwise, it is decided that the actual data 21 are not valid.
However, if the mirror data 22 and 23 are written to decide validity of the data, the capacity required to store the data increases, whereby waste of a space in the nonvolatile memory becomes a problem.
Furthermore, when the two mirror data 22 and 23 are written to write the actual data 21 of 1011000011, the data may incompletely be written as 1011110011 in the case of unexpected power failure. In this case, since the mirror data 22 and 23 are also written as 1011110011, it is decided that the data are valid in spite of the fact that the data are not valid. For this reason, a problem occurs in that validity of the data is decided in error.
The Korean Patent Unexamined Publication No. 2002-0010753 discloses a method of verifying validity of a memory using only simple memory access, which includes announcing a function located in a specific code area as a safe guard to verify validity of a user buffer, calling a buffer address check function which verifies validity, and deciding validity of a page to which the user buffer belongs. However, this related art fails to disclose a method of deciding data validity in the case of an unexpected power failure.